Field programmable analog arrays (FPAAs) are a relatively recent development in the electronics industry which enable a user to quickly and flexibly design and implement an extremely wide range of analog circuits. FIG. 1 shows an example of an FPAA comprising an array of individual, configurable analog blocks (CABs) 10 on a silicon chip 12. The CABs may be based on switched capacitor circuit technology, using capacitors which are integrated on silicon. A CAB might comprise a switched capacitor CMOS op amp, a comparator, an array of capacitors, CMOS switches and SRAM. The CABs are interconnected with configurable connections 14. Configurable Op amps 18, configurable band gap voltage references and other configurable analog elements are also dispersed across the chip. Configurable I/O blocks 20 and other configurable elements are disposed on the periphery of the chip. Configuration of all the configurable elements on the chip is carried out using configuration logic 16. The configuration logic provides an interface to a configuration data source and implements a mechanism by which configuration data is loaded into configurable elements on the chip, thereby defining the functionality of the FPAA.
Thus, by inputting user controllable configuration data to the FPAA, the FPAA can be programmed to replicate the functions of a large number of analog components or circuits, for example rectifiers, sample and hold circuits, filters, and level detectors. However, it is not possible to replicate the function of all circuits using a single FPAA, due to the finite number of resources available on a single FPAA. In principle, it is possible to solve this problem by utilizing a plurality of FPPAs interconnected in a “daisy chain”. In practice, the problems associated with conveniently loading data into such a daisy chain arrangement of FPAAs have been little explored. In one known arrangement (Zetex FAS TRAC), a plurality of FPAAs are ‘daisy chained’, each FPAA having a clock input pin, a data input pin and a data output pin. The data output of the first device is connected to the data input of the second device, the data output of the second device is connected to the data input of the third device, etc., and the clock pins are all connected together. To program the last device in the chain, data must be clocked through every register stage in each of the previous devices. In another known arrangement (LATTICE ISPPac), a plurality of field programmable analog devices are ‘daisy chained’ in a system in which each device is configured via a standard four pin JTAG interface. Following standard JTAG protocol, data to a particular device in a system must be clocked through a single register in each preceding device in a chain of JTAG devices.
A number of different methods are known for inputting data into various programmable logic devices such as field programmable gated arrays (FPGAs). Such devices differ structurally from FPAAs, since the latter are not logic devices. Nonetheless, the present inventors have recognized that certain programmable logic devices can comprise a number of unconfigured programmable units arranged in a daisy chain, which units are configured by loading data from a data stream.
One common method of transferring primary configuration data to programmable logic devices is to use a clocked serial EPROM to transfer data serially down into the programmable devices. Another method is to use a serial interface to an external device which is used to download serial configuration data. In both methods the problem to be solved is that of ensuring that a concatenated primary configuration bitstream is applied correctly to the programmable devices, with the correct section of the bitstream being supplied to the right device. If reconfiguration is supported, then once primary configuration is complete, the same interface must be used to support reconfiguration.
A number of methods have been developed for ensuring that the serial bitstream is supplied to the correct programmable device.
One method comprises providing a chip select pin to each device and to synchronize the assertion of the chip select pin with the arrival of the correct portion of the configuration bitstream. This method is, however, inefficient, as it requires that there be N chip select tracks routed through a system comprising N programmable devices. In addition, there is a software and hardware processing overhead introduced by the synchronizing mechanism.
A second method is to route the serial bitstream through each device in the chain. In this system data arrive on the first device in the chain on a DIN pin, and leaves via a DOUT pin, which is connected to the DIN pin of the second device in the chain. The connections continue in this manner over as many devices as there are in the chain. The system is arranged such that data are loaded serially into the first device which begins configuring. Until the device has configured, data are inhibited from passing through to DOUT and therefore the second device sees no data. Once the first device has configured, data on the DIN pin are effectively routed directly to the DOUT pin via a single register stage and the second device then inputs data via the DIN pin and begins to configure. Likewise the second device inhibits data from passing to its DOUT pin until configuration is complete. The method, however, has the disadvantage of being slow, since data being targeted at the last device in the chain must first be clocked through all preceding devices. Another approach to this problem is given in U.S. Pat. No. 5,696,454, where the problem of having to clock data through preceding devices is minimized by utilizing a ‘local count’ byte in the configuration bitstream, which, if set to zero, allows a device to be bypassed using a single register stage as before. In the case where only part of the device is to be configured a ‘remainder count’ byte is utilized which is used to determine the amount of configuration data to be loaded into a particular device before bypassing takes place. There will, however, still be a pipelining delay through a chain since each device must evaluate and process the ‘local count’ byte and ‘remainder byte’ (and associated data bytes) before bypassing takes place.
This pipelining disadvantage is a particular handicap if the methodology is used subsequently to try and selectively reconfigure particular devices in a chain, since data must first be routed through all preceding devices. A general approach when reconfiguration is required is to reconfigure all the devices in the chain including those that do not actually need updating.
In a third, token based, method, token based method data are applied in parallel to all of the programmble devices, and a token is passed from one device to the next in the chain as each one becomes programmed. The token enables the next device to start receiving configuration data. Loading of data is controlled by controlling the configuration clock.
U.S. Pat. No. 5,640,106 and U.S. Pat. No. 5,838,167 describe a further token based method in which two separate enable signals are used for configuration. One of the enables, EN2, is common between all devices in a system, and can be used to enable and disable the primary configuration process for all devices in the system. The other enable, EN1, is used to initiate configuration of a first device. Once configuration of the first device is complete, the first device asserts an output signal which is used to enable EN1 on a second device, which then starts to configure. This process carries on ad-infinitum with the enabling ‘token’ being passed to the next device in the chain once the previous device is configured. The clock in this system is not used directly to control the configuration process, and by implication is continuous.